China's DFSX is working on fueling its domestic AI supply chain with next-gen 3.5D "Infinity Chiplet" architectures & 3D DRAM technologies.

DFSX Is Working on China's First DF1000 AI Accelerator With 3D DRAM Technology, Also Unveils 3.5D+ Packaging

DFSX recently hosted a presentation where they announced China's first 3D AI chip that is built entirely using China's domestic supply chain. There is a lot to unpack here, but the key product is the DF1000, which is a software-defined near-in-memory computing AI accelerator that will be used by domestic AI and tech firms.

DF1000 – China's First 3D DRAM-Powered AI Accelerator Made Using a Domestic Supply Chain

Starting with the details, the DF1000 chip is based on a 14nm process technology and packs 520 TFLOPs of BF16 compute. The main talking point about this chip is that it leverages 3D DRAM with in-memory processing capabilities.

The 3D DRAM is stacked using hybrid bonding technology and offers increased memory capacity, bandwidth, and density through wafer-level stacking. Current figures highlight up to 6.4 TB/s of memory access bandwidth & a scale-up interconnect bandwidth of 900 GB/s.

The company states that the use of hybrid bonding compresses the interconnect pitch down from micrometers to sub-micrometer levels, boosting interconnect density and bandwidth density while reducing power consumption, compared to traditional interconnect solutions. 3D Stacking also increases the TSVs by 10x, boosting bandwidth by 5x on the same capacity. These provide a great alternative to HBM processes.

With 3D DRAM, DFSX bypasses the HBM memory wall and dependency on the overseas HBM supply chain and more expensive manufacturing processes, while retaining higher bandwidth, capacity & getting an advantage in terms of cost.

Some salient features of the DF1000 chip include:

• Software-Defined Ultra-High-Performance Near-Memory Computing 3D Chip: Based on "software-defined chip" and "near-memory computing" technologies and mature domestic processes, this chip delivers high performance, high energy efficiency, and high flexibility.
• Basic Software and Application Ecosystem: Constructing an independent and open software stack and toolchain, providing a one-stop solution for distributed training and inference of mainstream large-scale models.
• High-Performance Servers: Providing rapidly deployable high-performance servers with a pre-installed complete software stack, compatible with mainstream deep learning frameworks and large-scale applications.

DFSX isn't sharing much data on performance, but internal estimates show performance matching or surpassing NVIDIA's Hopper H200 GPUs. Interestingly, the first H200 shipments are already on their way to China. DF100 offers twice the bandwidth of the Hopper H100 chip and 33% more bandwidth than H200. The chip can reach 500 Tokens/s in Llama3 70B models, while TPOT was recorded at 20ms in DeepSeek-3.2.

Infinity Chiplet "3.5D" Architecture For Future Chips

As China faces massive curbs on advanced packaging and process technologies, domestic firms are coming up with new ways to utilize mature process technologies such as 14nm (used by the DF1000 chip) to accelerate their AI developments.

Infinity Chiplet is DFSX's answer to the problem, a 3.5D+ (multi-chip 3.5D stacked package) that leverages three key fundamentals. First is the 3.5D stacking to replace data storage structures, saving chip area and providing greater bandwidth within the same area. The second is to cut off HBM use by leveraging 3D DRAM, and the third is to enhance I/O power characteristics by making full use of the exclusion of HBM memory.

The Roadmap Ahead – DF2000 Production In Q4 2026, DF3000 In Q4 2027

Following the DF1000, which is now shipping, DFSX will introduce its DF2000 chip by early 2027, which will offer 1000 TFLOPs of BF16, 2000 TFLOPs of FP8, 4000 TFLOPs of FP4 compute, 15 TB/s bandwidth using an advanced 3D DRAM design, & 1600 GB/s of scale-up interconnect bandwidth. The DF2000 accelerator will also utilize a 14nm process technology.

The company has also outlined the DF3000, which will enter markets in 2028, offering twice the compute capabilities of DF2000 at 2000 TFLOPs of BF16, 4000 TFLOPs of FP8, 8000 TFLOPs of FP4, 20 TB/s bandwidth, and 3200 GB/s interconnect bandwidth.

The DF2000 AI accelerators are expected to surpass the performance levels of NVIDIA Hopper GPUs and will be able to reach Blackwell levels, while DF3000 is said to compete against NVIDIA Blackwell big time.

DF1000 is already being deployed in large-scale racks and PODs using the standard OAM 2.0 interface. The tray includes up to 8 DF1000 AI accelerators, and Zhaoxin has also partnered with the company to adapt its server chips to the platform. The primary node offers 4.16 PFLOPs of FP16 compute, 51.2 TB/s of bandwidth, 7200 GB/s of Scale-Up bandwidth, 3.2 Tbps of Scale-Out bandwidth, a power consumption of 12KW, and a 120-core CPU. The racks start at 64 and scale up to 512 hyperscaler designs.

News Source: EET-China

About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.

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