Cadence Design Systems, Inc. (Nasdaq:CDN) and the Shanghai Research Center For Integrated Circuit Design (ICC), China's first national integrated circuit (IC) design industrialization base founded by China's Ministry of Science and Technology, today announced the availability of the ICC-Cadence CPU/digital signal processing (DSP) system-on-chip (SoC) reference methodology.

The reference methodology, which includes the Cadence Encounter digital implementation platform, Incisive functional verification platform and CoWare software tools for electronic system-level design and verification, is the first to offer rapid and predictable implementation of SoC chip designs for the expanding IC industry in China.

Based on the Cadence Encounter digital IC design and Incisive functional verification platforms, the reference methodology was built upon CPU and DSP cores from leading processor IP providers. The implementation flow was validated with several leading foundries on their 0.18-micron processes. The tools supported in the reference methodology include NC-Sim, Conformal-ASIC, Nano Encounter, CeltIC, Fire & Ice QXC, VoltageStorm, SignalStorm and CoWare ConvergenSC Advanced System Designer through a Cadence and CoWare strategic partnership.


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