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A Massive Development: AMD's Magnificently Dominant Zen 6 EPYC Venice arrives with 256 cores, outclassing NVIDIA in hardware, specs and leadership

AMD spent two days in Las Vegas taking the lid off its sixth-generation server chip. The headline is 256 cores in one socket. The better story is how the dense core stopped being the budget option, what the fine print says, and how the week ended for AMD and Nvidia.

AMD's 6th Gen EPYC processors, codenamed Venice and built on the new Zen 6 architecture, are now generally available. SP7 platforms started shipping from server makers on 10 November 2026, US time.

The flagship EPYC 9996 packs 256 cores and 512 threads into one socket at up to 600W. It lists at US$14,904 in 1,000-unit lots, according to the pricing table in AMD's launch announcement.

"AI is significantly expanding the role of the CPU across every layer of the data centre," said AMD Senior Vice President and General Manager, Compute and Enterprise AI, Dan McNamara, in that announcement.

The first presentation on day one of AMD In Depth, held in Las Vegas on 4 November under a six-day embargo, ran to 86 slides. This article covers the opening keynote sessions: the welcome, the Zen 6 core, and the Venice system-on-chip.

More articles covering the platform, memory, security and partner sessions get their own articles, with the link to each to be added as each article appears, at the end of this article.

The short version

  • Up to 256 Zen 6c cores or 96 Zen 6 cores per socket, with two threads per core on both

  • Compute dies built on TSMC's 2nm process

  • A new SP7 socket with 16 DDR5 memory channels and up to 1.6TB/s of memory bandwidth

  • PCIe Gen 6 and CXL 3.1

  • Roughly 27% more instructions per clock than Zen 5, with caveats I'll get to

  • Three more family members due in 2027: Venice SP8, Venice-X and Verano

A company that started the year in the low 40s

The welcome came from AMD Corporate Vice President, Compute and Enterprise AI Product Group, Madhu Rangarajan, who went straight to the scoreboard.

"We started off this year in the lower 40% in market share, and we are now in the mid 40s. We expect to finish the year even higher," said Rangarajan.

The independent numbers agree. Mercury Research had AMD at a record 46.2% of x86 server CPU revenue in Q1 2026 on 33.2% of units.

From the first EPYC 7601 in 2017 to the EPYC 9996, AMD's chart shows 19.9 times the throughput per chip, and last generation's 192-core EPYC 9965 sits at 10.1 on the same line. That's close to a doubling in one generation.

Against Turin, the fifth generation, AMD claims 2.0x on SPECint 2026, 2.4x on SPECfp 2026, 2.7x on the STREAM memory test, 1.4x on HPL and 1.3x on DGEMM.

Rangarajan's reason for caring about that breadth was the agent story. "Agents are doing all kinds of things. They're running EDA workload. They're running CRM workload. They're running HPC," he said.

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Zen 6 was designed before anyone said 'agentic'

The most refreshing line of the day came from AMD Corporate Fellow, Senior Vice President and Lead Zen Architect, Mike Clark, who has been at AMD since 1993 and drew the original Zen.

"I'm not going to mislead and act like I knew agentic computing was coming," said Clark. "But we did strongly believe that the CPU would always have a place in the software ecosystem of AI."

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That matters because Nvidia's Vera and Arm's AGI CPU are both being sold as agent-first designs. AMD's pitch is that a strong general-purpose core, built in volume, happens to be what agents need, since an agent spends its day calling tools, compiling code and querying databases.

Zen 6 comes in two physical layouts of the same core. Zen 6c is the dense version, tuned for throughput. Zen 6 is the high-frequency version, tuned for latency.

The dense core gets promoted

This is the part I think gets lost under the 256-core headline.

In the last generation, the "c" core was the compromise. Zen 5c had 16 cores sharing 32MB of L3 cache, or 2MB per core, half what the full-size core got, and it topped out at 3.7GHz.

Zen 6c doubles the complex to 32 cores and quadruples the cache to 128MB, restoring the full 4MB per core. Maximum frequency rises to 4.1GHz.

Both layouts now come off the same TSMC 2nm line, where Zen 5 and Zen 5c were split across older and newer nodes. AMD has even added a spare core to each 32-core die to lift yield.

"This is truly a first-class citizen in terms of performance cores," said AMD Senior Fellow and Corporate Vice President, Server Architecture, Mahesh Subramony.

In one respect the dense core is now the bigger machine. Its floating-point schedulers hold 60 entries each against 46 on the high-frequency core, because a design that only has to reach 4.1GHz can afford larger structures than one chasing 5.3GHz.

The high-frequency core moves from eight to 12 cores per die, from 32MB to 48MB of L3, and from 5.0GHz to 5.3GHz, for a ceiling of 96 cores per socket.

Software sees one architecture. Clark said there are slight IPC differences between the two and zero instruction set differences, and both support two threads per core.

What changed inside the core

Zen 5 was the rebuild. Zen 6 is the generation where AMD sanded down everything it learned from that rebuild.

The reorder buffer, which sets how many instructions can be in flight at once, grows from 448 entries to 640. That's 43% more room to find work that can run in parallel.

Around it, the integer register file goes from 240 to 352 entries, the load queue from 64 to 80 and the store queue from 96 to 128.

The op cache now holds 6,750 ops and can feed 18 per cycle to the back end, up from 12 instructions.

"Architecture has to be balanced. We can't just grow one part of the machine without balancing it out across the whole machine," said Clark.

For AI work, Zen 6 adds full AVX-512 FP16 arithmetic (Zen 5 could only convert the 16-bit format, then do the maths in 32-bit), and doubles the VNNI INT8 pipes from two to four.

The quietly significant addition is FRED, a new interface for interrupts, exceptions and system calls that AMD and Intel developed together with operating system vendors. Clark humorously called it "well-named", and said the old mechanism had barely changed since AMD64 and carried security problems software kept having to patch around.

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The 27% claim, and how AMD got there

AMD says Zen 6c delivers about 20% more IPC than Zen 5 on enterprise and cloud workloads, about 31% on AI workloads, and roughly 27% across the lot.

Read the method before you quote it. AMD fixed the frequency and ran 16-core workloads, which on Zen 5 straddle two eight-core dies and on Zen 6c sit inside one 32-core die with four times the shared cache.

So the figure blends core improvements with the benefit of the bigger complex. That's a fair picture of what a customer will see, and a generous one if you wanted a pure core-versus-core number.

Clark, to his credit, said so on stage: "Feel free to do it a different way if you like."

Inside the SoC: two I/O dies and a lot of packaging

Subramony's session covered how the cores become a product.

A Venice SP7 chip carries up to eight compute dies around two identical I/O dies, the second rotated 180 degrees. Every compute die sits within a few hundred microns of an I/O die.

That closeness is the big change from Turin. The old long-reach links between dies have been replaced by elevated fanout bridges, an advanced packaging technique built with TSMC that cuts the energy spent per bit moved.

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The SP7 socket supports 16 channels of DDR5-8000, or MRDIMMs at 12,800MT/s, for a theoretical 1.6TB/s per socket. Turin managed 614GB/s, so that's about 2.6 times the bandwidth.

Maximum memory is 8TB per socket with 512GB modules. "If you can find it these days," said Subramony.

On I/O, a single-socket SP7 server gets 96 lanes of PCIe Gen 6 at 64Gbps each, and a dual-socket server gets up to 128. Turin offered 128 Gen 5 lanes in one socket, so the lane count falls while total bandwidth rises by half.

Power per core is the real spec sheet

Subramony showed a chart I'd frame and hang in every procurement office. It breaks Venice into three operating ranges by watts per core.

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  • Bulk agentic: 256 cores at 400W, between 1.2W and 2.0W per core, tuned for threads per megawatt

  • Cloud: 256 cores at 600W, between 1.7W and 3.5W per core, tuned for peak throughput and cost

  • HPC and AI head nodes: 96 cores at 500W to 600W, between 5W and more than 10W per core, tuned for bursts

The logic is that servers rarely run flat out. When only 30% of a cloud chip's cores are busy, the power budget pools across them, and that's why even the dense core had to reach 4.1GHz.

Three more chips are coming

Venice SP7 is the first of four.

Venice SP8 is the enterprise part: a smaller 62.5mm by 80mm socket, a 400W ceiling, eight memory channels with two DIMMs each, and up to 128 Zen 6c or 96 Zen 6 cores. It trades memory bandwidth for I/O, with 128 PCIe Gen 6 lanes in one socket and 192 in two.

Venice-X stacks 3D V-Cache on the 12-core dies for 144MB each, or 1,152MB of L3 per socket, for cache-hungry HPC codes.

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Verano is the new one. It pairs up to 192 Zen 6c or 72 Zen 6 cores with 24 channels of LPDDR5X on field-replaceable SOCAMM modules, attached through four small memory dies AMD calls winglets, in a single-socket package of up to 500W.

Low-power memory is how Nvidia's Vera earns its efficiency numbers, so Verano reads as AMD's direct reply. "We have another arrow in the quiver," said Subramony.

TechPowerUp reported in July that SP8 is due in the first half of 2027, with Venice-X and the low-power parts in the second half.

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Security gets cheaper to switch on

"The world continues to feel more insecure, so confidential compute capabilities are essential," said Clark.

The Zen 6 work here is about reducing the performance tax. Ordinary virtual machines sharing a host with SEV-SNP confidential guests now pay a smaller penalty, live migration of confidential guests is faster, and confidential guests can keep both threads of a core.

The root of trust adds post-quantum cryptography support, which will interest anyone writing a sovereign cloud tender.

How it stacks up, and who's checking

AMD's own comparisons use published SPECrate 2017 integer scores: 5,470 for a two-socket EPYC 9996 server against 2,510 for Intel's Xeon 6980P. That's 2.2 times the performance and, on list prices, twice the performance per dollar.

The "up to 3.7x" figure against Nvidia's 88-core Vera rests on a score AMD estimated itself, as its footnotes disclose. Treat it accordingly.

Independent testing is in, on AMD-supplied systems. Tom's Hardware measured a dual EPYC 9996 server 93% ahead of its predecessor on integer throughput, and the 96-core EPYC 9686F ahead of Vera by 17% on integer and 40% on floating-point work.

Vera kept some wins, including several memory tests and cold-cache database queries, and the review published no measured power figures. Its author still called AMD's lead "difficult to ignore".

Intel's answer is Diamond Rapids, the Xeon 7, which slipped to 2027. Intel has said it will match Venice at 256 cores, with one thread per core where AMD has two.

AMD also says its unified power provisioning feature fits about 18% more agents into a 35kW rack by budgeting CPU and memory power together. The footnote notes the performance cost was measured on a previous-generation chip, so I'd want to see that repeated on Venice.

A CEO of the year, and a rival without one

Launch week ended with a contrast that wasn't on any slide.

On 12 November, Yahoo Finance named AMD Chair and Chief Executive Officer, Dr Lisa Su, its 2026 CEO of the Year, pointing to a share price up 158% this year. Su told the outlet she joined AMD to work at "the bleeding edge of technology".

The same day, Nvidia announced that co-founder Jensen Huang had resigned as president, CEO and director after 33 years, effective immediately. Does that make him ZErO of the year? It would definitely seem so. 

Nvidia Executive Vice President and Chief Financial Officer, Colette Kress, is interim CEO while the board searches for a successor.

Nvidia's statement gave no reason. The Washington Post and others report it followed revelations about Huang's personal relationships and investigations into whether he was a target of foreign intelligence, from an alleged Chinese spy, to then an alleged relationship with an Nvidia subordinate, and then allegations of a third! No findings have been announced.

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On CPUs, AMD's lead over Nvidia is real. Vera has 88 cores to Venice's 256, the 96-core EPYC 9686F beat it in most independent tests, and Nvidia sells one server CPU where AMD is building a family of four.

AMD's position is the strongest it has ever been. Its Q3 2026 results showed record revenue of US$13.4 billion and data centre sales of US$8.5 billion, up 97%, on top of that record share of server CPU revenue.

Keep the scale in view, though. Zen 6 is a CPU, and Nvidia's business is built on GPUs, where it remains far larger. The Next Platform reckons agentic AI won't be enough for AMD to catch Nvidia there, and Nvidia reports its own quarter on 17 November.

The week's other reminder: Microsoft's outage

The same week delivered a lesson in what all this silicon is for. A Microsoft 365 outage that began on 12 November US time took Outlook, Teams and Copilot down for close to 24 hours, and Microsoft now reports "broad recovery and stability", blaming a fault introduced in an earlier network capacity upgrade. AI went down with it: Anthropic said Claude for Outlook and Claude's Microsoft 365 connector were failing on email, calendar and search, and ChatGPT's Microsoft integrations had the same trouble (I covered the outage here).

Here's my speculation, and it's only that. I think this outage speeds up three things: AI agents that watch telemetry and roll back a bad change in minutes, AI that rehearses a configuration change against a model of the network before it ships, and designs with fewer shared chokepoints, so a fault stays local and the system builds something like immunity. All of that is CPU-heavy agent work, which is the job Venice was just launched to do, and the agents doing it will need the same redundancy as everything else.

What this means for Australian buyers

Power is the Australian constraint. We're the world's third-largest data centre market, AEMO expects a seven-fold rise in data centre power use within a decade, and operators are now expected to fund their own grid connections.

In that setting, the 400W, 256-core configuration is probably the one to watch, more than the 600W flagship. Threads per megawatt is a metric a facilities manager can take to a board.

Licensing is the other catch. Plenty of enterprise software is priced per core, and Broadcom's VMware subscriptions carry core minimums. A two-socket EPYC 9996 server is 512 licensable cores, and I think that's part of why the 96-core, 5.3GHz parts exist.

Most Australian organisations will meet Venice in the cloud first. Microsoft's Azure HDv2 instances are in preview, Oracle's OCI Compute E7 is on the way, and Meta is validating the platform as a lead customer.

More from AMD In Depth

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This article was written and researched with AI assistance, using personally created and/or recorded original material, supplied material and that from online sources and the Internet at large, then further edited, improved and published by Alex Zaharov-Reutt.

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