Synopsys, Inc., the semiconductor design software company, and Shanghai Huahong NEC (HHNEC) Electronics Co. Ltd., one of China's integrated circuit (IC) manufacturers, today announced that the two companies have jointly developed and delivered a new reference design flow, for HHNEC's 0.25-micron silicon process, for mutual customers.

The validated flow is based on Synopsys Galaxy Design Platform and HHNEC's I/O and 0.25-micron standard cell libraries. Designers can request the design flow from HHNEC and immediately begin using Synopsys' proven methodology–based on best-in-class design tools–to help solve the timing closure challenges of complex system-on-chip (SoC) designs, help shorten design cycles, and ensure faster time-to-volume.

The RTL-to GDSII flow, which is now complete, was created to provide a systematic approach in three stages to address the typical design steps in SoC designs. In the first stage, design synthesis, Design Compiler and DFT Compiler were used to create a gate-level netlist for a design. Astro and Physical Compiler were used for place and route in the second stage, design implementation. In the third stage, design optimization and sign-off, PrimeTime with Star-RCXT was used for timing analysis with accurate parasitics, Astro for design optimization and chip finishing to achieve timing closure, and Hercules for physical verification and sign-off of GDSII before tape-out to HHNEC.

The Galaxy Design Platform is an open, integrated design implementation platform with best-in-class tools and IP, enabling advanced semiconductor design. Anchored by Synopsys' industry-leading semiconductor implementation tools and the open Milkyway database, the Galaxy Design Platform incorporates consistent timing, signal integrity (SI) analysis, common libraries, delay calculation, constraints, testability, and physical verification from RTL all the way to silicon.