In the global semiconductor race, the competition often centers on achieving smaller process nodes, with headlines celebrating breakthroughs in 3-nanometer and 2-nanometer manufacturing. However, a prominent Chinese chip executive is challenging that narrative, arguing that raw system performance matters far more than the nominal nanometer label assigned to silicon.
Dr. Xie Zhifeng, a co-founder of Semiconductor Manufacturing International Corporation (SMIC), shared these insights during a recently published conversation with Fudan University researcher Zhao Xin in Chinese media. According to Xie, achieving target computing performance is the true benchmark of success, regardless of the manufacturing techniques used to get there.
To slow China’s military modernization and maintain leadership in artificial intelligence, the United States, alongside key allies like the Netherlands and Japan, has enacted a comprehensive web of export controls restricting Chinese access to advanced semiconductor technology. Initiated in October 2022 and progressively tightened through subsequent updates, these restrictions prohibit the transfer of high-performance artificial intelligence chips, advanced electronic design automation software, and crucial manufacturing equipment, such as extreme ultraviolet lithography systems.
When access to extreme ultraviolet (EUV) lithography equipment is restricted, Chinese chipmakers are forced to find alternative engineering pathways. Xie noted that China’s domestic logic chips, which power CPUs and GPUs, are currently delivering performance equivalent to 7-nanometer and 5-nanometer levels.
Rather than adopting standard nanometer branding for these advanced iterations, SMIC uses internal designations starting from 14-nanometer and progressing through N+1, N+2, and N+3 pathways. Xie emphasized that if a system delivers the necessary processing speed and efficiency, the specific marketing name attached to the chip process becomes secondary.
To achieve advanced performance levels without EUV tools, engineers creatively rely on techniques such as deep ultraviolet (DUV) multi-patterning and three-dimensional chip stacking.
Multi-patterning on DUV equipment involves running multiple exposure passes to etch finer circuit patterns. While effective at producing equivalent 7-nanometer or 5-nanometer performance, Xie acknowledged that the process has clear trade-offs. Multi-patterning lengthens manufacturing timelines and significantly increases production costs, making it less ideal for high-volume consumer production, though highly viable for specialized batches.
Complementing this approach is advanced 3D packaging and system-level optimization. Strategies that focus on reducing latency across the chip, package, and overall system allow manufacturers to boost real-world performance without relying entirely on smaller physical transistor gates.
Xie also cautioned against a common misconception in the tech industry: the assumption that a smaller process node automatically guarantees a superior user experience. He pointed out that certain commercial processors built on advanced 5-nanometer and 4-nanometer nodes have historically faced thermal management and efficiency challenges in real-world applications.
Ultimately, Xie expressed confidence in the ability of China's domestic engineers to innovate within existing global blockades and constraints. By prioritizing system-level integration and practical performance over process node specs, manufacturers aim to deliver chips that meet customer needs regardless of the toolsets used to build them. While these measures by the United States, Netherlands, and Japan have severely limited China's ability to mass-produce chips below the 7-nanometer threshold, they have apparently simultaneously catalyzed a massive, state-subsidized push across Chinese industry to develop indigenous semiconductor supply chains, pioneer advanced packaging solutions, and achieve long-term technological self-reliance.
