Another week brings another anecdote of how China's CXMT is seemingly leveraging its newfound tech prowess to give the so-called Big Three memory players – Samsung, SK hynix, and Micron – a run for their money.
Even so, the latest anecdote is quite ambitious in its scope, delineating how CXMT is gearing up to leapfrog Samsung by around 2 years on the next-gen 4F² memory cell architecture.
CXMT is now gunning to introduce a server-geared memory product that leverages an entirely new memory cell architecture by the end of 2026, while Samsung intends to produce memory products on this new architecture only in 2028
To wit, CXMT's President, Dr. Cao Kanyu, recently delivered a speech at the 4th Integrated Chip and Chiplet Conference in Shanghai, discussing CXMT’s progress on the next-gen 4F² DRAM architecture as well as other innovative technologies such as hybrid bonding.
During the speech, Dr. Kanyu declared that CXMT will introduce a DDR5 RDIMM product based on the 4F² memory cell architecture before the end of 2026, which is around two years ahead of Samsung's roadmap for the introduction of this architecture.
For the benefit of those who might not be aware, the Registered Dual In-Line Memory Module (RDIMM) acts as a hardware buffer that holds the oncoming signals from the CPU for precisely one clock cycle before sending them onward to the memory chips, reducing electrical load and enabling server operators to plug in a higher number of high-capacity sticks of RAM into a single motherboard.
Meanwhile, the 4F² process is a next-generation memory cell architecture, where the components of a single memory cell (one transistor and one capacitor) are stacked vertically rather than horizontally. This design shift reduces the surface footprint of a single memory cell to a perfect square, which measures 4 times the minimum feature size squared (4 × F²), and consists of exactly 2 bitlines and 2 wordlines. Do note that bitlines and wordlines are the interconnect structures used to operate the transistors within each memory cell. Just by changing the structure to 4F², DRAM makers are able to increase the cell density of each IC by 30 – 50 percent.
Of course, CXMT has been exploring this technology for a number of years, having published its first paper on the 4F² architecture back in 2021. Also, by going from a 6F² to 4F² architecture, CXMT would be able to cut the memory cell area by around 33 percent at the same feature size, necessitating new transistors. Even so, it is quite likely that CXMT's initial implementation would be a partial derivative of the 4F² architecture on its new 15nm G5 DRAM process.
What's more, to overcome process miniaturization constraints, CXMT is now apparently using High-k Metal Gate or HKMG technology, which replaces the old silicon-based insulator with a material like hafnium oxide (HfO?), not only curbing current leakage and the attendant waste thermal energy, but also enhancing power efficiency and paving the way for higher speeds, as the transistors are able to flip states much faster than what would have been possible via polysilicon gates. CXMT is now apparently applying this technology to its G4 DRAM fabrication process – which is widely believed to be on the 1z node – as well as LPDDR5X products.
Do note that CXMT is aggressively expanding its capacity right now, to the tune of 300,000 wafers per month – via three 300mm DRAM fabs with a capacity of ~100,000 wafers per month each – by the end of this year. It will also have an HBM-focused capacity of around 50,000 wafers per month by the end of 2026.
What's more, the memory maker is currently building two new fabs in Shanghai and Hefei, which would increase its production capacity to 600,000 wafers per month. In fact, CXMT is now on course to overtake Micron in volume production by 2030.
Elsewhere, Samsung will likely introduce the 4F² architecture with its B1b process – its first sub-10nm DRAM fabrication process and officially renamed D0a – where the memory cells and the surrounding driver circuitry, known as the peri, will be fabricated on separate wafers and then joined together via wafer-to-wafer hybrid bonding, thereby stacking the memory cells on top of the peri. Because hybrid bonding is quite expensive, it is only reasonable to assume that Samsung will price the next-gen DRAM at an eye-watering premium.
About the author: Writing is my one incontrovertible passion. Over the past six years, he has authored over 2,200 distinct articles on financial and tech-related topics, spanning nearly 1 million words. And he has been a member of Wcctech mobile team since 2025.
As an alumnus of the University of Toronto, Rotman Commerce Program, I bring nuance, in-depth knowledge, and a unique perspective to every topic that I cover.
When I'm not writing, I'm traveling the world, exploring hidden confectionaries and restaurants as an aspiring food connoisseur.
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